Chips today are very complex devices, often having tens of thousands of transistors, if not hundreds of thousands or millions of transistors, that comprise complicated logic circuits and functionality. Although any bug in a chip or functionality not specified for the original chip can theoretically be worked around by external circuitry, practically speaking, only the simplest of these can be fixed externally because of the large amount of external circuitry that may be required. Therefore, when a hardware bug is found in a chip, great cost may be incurred in redesigning, laying out and manufacturing a new chip. Production of a system, of which the chip may be an integral part, may potentially be delayed by several months while waiting for the new chip, with even more cost incurred resulting from lost sales.
Conventional chips may provide the capability to observe critical internal logic signals on external pins for debugging purposes. These signals may be referred to as debug signals and may be accessible via a debug bus or debug port. A chip designer may also provide external access to at least the most important signals associated with the different hardware functions or blocks in the chip, since access to these signals may also be helpful during debugging.
FIG. 1 is a block diagram of a typical architecture of an exemplary chip with an embedded processor. Referring to FIG. 1, there is shown a processor 102, an interrupt controller block 104, a memory block 106, a control register block 108, a plurality of functions 110, 112, 114, a debug port multiplexer 116, a plurality of debug pins 120 and a plurality of general purpose I/O (GPIO) pins 122. The interrupt controller block 104 may comprise an interrupt controller register (ICR) 124. The functions may comprise Function_1 110, Function_2 112 and Function_n 114.
The processor 102 may be an embedded processor such as an ARM processor. The interrupt controller 104 may comprise suitable logic, circuitry and/or code that may be adapted to provide an interrupt signal INT to the processor 102, which indicates that certain functionality may have been completed or that there may be a problem that may require the attention of the processor 102. The memory 106 may be dynamic random access memory (DRAM), read-only memory (ROM), a non-volatile writeable random access memory (FLASH), and/or other types of memory. The functions 110, 112, 114 may comprise suitable logic, circuitry and/or code that may be adapted to perform specific functionalities needed for this system such as, for example, video processing, audio processing, or data encryption/decryption, as well as general functionalities needed for the chip to operate. The control register 108 may comprise suitable logic, circuitry and/or code that may be adapted to control the output of the debug signals from the debug ports multiplexer 116 to the debug pins 120. The multiplexer 116 may comprise suitable logic, circuitry and/or code that may be adapted to select which of the inputs from the functions 110, 112, 114 may be output to the debug pins 120.
The GPIO pins 122 may be coupled to functionality external to the chip, which may be adapted to provide input signals to the chip and/or receive output signals from the chip. The functionality of the GPIO pins 122 may be controlled by the control register block 108. The ICR 124 may comprise suitable logic, circuitry, and/or code that may be adapted to control occurrence and/or handling of interrupts by the interrupt controller 104.
In the exemplary system of FIG. 1, the processor 102 may execute instructions and/or use data in memory block 106, and may respond to at least one interrupt signal referred to as INT from the interrupt controller 104. The processor 102 may additionally control the functionality of the interrupt controller 104, may read and/or write to the control register block 108 in order to output the correct debug signals from the debug port multiplexer 116, and may control the functionality of the functions 110-114. The interrupt controller 104 may receive interrupt signals from the functions 110-114, and may generate the interrupt signal INT to the processor 102.
If a hardware bug exists in the exemplary system illustrated in FIG. 1, and the bug must be fixed, the only option may be to re-design the chip to remove the bug, and re-spin the chip.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.